The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
Regular Ternary Logic Functions Ternary Logic Functions Suitable for Treating Ambiguity
IEEE Transactions on Computers
IEEE Transactions on Computers
A unified framework for race analysis of asynchronous networks
Journal of the ACM (JACM)
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Mapping switch-level simulation onto gate-level hardware accelerators
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Transistor level test generation for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
Formal Methods in System Design
Some algebraic and combinatorial aspects of Multiple-valued circuits
MVL '76 Proceedings of the sixth international symposium on Multiple-valued logic
Microprogrammed operations for a three-value logic simulator
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
An accurate time delay model for large digital network simulation
DAC '76 Proceedings of the 13th Design Automation Conference
Hazard detection by a quinary simulation of logic devices with bounded propagation delays
DAC '72 Proceedings of the 9th Design Automation Workshop
Ternary logic in digital computers
DAC '65 Proceedings of the SHARE design automation project
Beyond two
Fast hazard detection in combinational circuits
Proceedings of the 41st annual Design Automation Conference
A halfbaked idea about a set of register transfer primitives: (part 1)
ACM SIGMICRO Newsletter
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
A Unified Approach to Combinational Hazards
IEEE Transactions on Computers
An Algebraic Model for the Analysis of Logical Circuits
IEEE Transactions on Computers
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A Simplified General Method for Static Hazard Detection
IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis
IEEE Transactions on Computers
Simulation of large asynchronous logic circuits using an ambiguous gate model
AFIPS '71 (Fall) Proceedings of the November 16-18, 1971, fall joint computer conference
The analysis of cyclic circuits with Boolean satisfiability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A three-value computer design verification system
IBM Systems Journal
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Hazard-based detection conditions for improved transition fault coverage of scan-based tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hazard-based detection conditions for improved transition path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.04 |
This paper is concerned with the study of static hazards in combinational switching circuits by means of a suitable ternary switching algebra. Techniques for hazard detection and elimination are developed which are analogous to the Huffman-McCluskey procedures. However, gate and series-parallel contact networks are treated by algebraic methods exclusively, whereas a topological approach is applied to non-series-parallel contact networks only. Moreover, the paper derives necessary and sufficient conditions for a ternary function to adequately describe the steady-state and static hazard behavior of a combinational network. The sufficiency of these conditions is proved constructively leading to a method for the synthesis of combinational networks containing static hazards as specified. The section on non-series-parallel contact networks also includes a brief discussion of the applicability of lattice matrix theory to hazard detection. Finally, hazard prevention in contact networks by suitable contact sequencing techniques is discussed and a ternary map method for the synthesis of such networks is explained.