Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
Proceedings of the 39th annual Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Hazard detection by a quinary simulation of logic devices with bounded propagation delays
DAC '72 Proceedings of the 9th Design Automation Workshop
Automatic Synthesis of Burst-Mode Asynchronous Controllers
Automatic Synthesis of Burst-Mode Asynchronous Controllers
Three generations of asynchronous microprocessors
IEEE Design & Test
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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In designing asynchronous circuits it is critical to ensure that cir-cuits are free of hazards in the specified set of input transitions. In this paper, two new algorithms are proposed to determine if a com-binational circuit is hazard-free without exploring all its gates, thus providing more efficient hazard detection. Experimental results in-dicate that the best new algorithm on average visits only 20.7% of the original gates, with an average runtime speedup of 1.69 and best speedup of 2.27 (for the largest example.