Fast hazard detection in combinational circuits
Proceedings of the 41st annual Design Automation Conference
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent rewriting semantics and analysis of asynchronous digital circuits
WRLA'10 Proceedings of the 8th international conference on Rewriting logic and its applications
Back annotation in high speed asynchronous design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The asynchronous circuits we use are called quasidelay-insensitive (QDI) circuits. A QDI circuit involves no assumption about, or knowledge of, delays in operators and wires, except for isochronic forks, which the designer assumes have similar delays on the different branches. QDI circuits are the most conservative asynchronous circuits in terms of delays.