Correspondence between ternary simulation and binary race analysis in gate networks
International Colloquium on Automata, Languages and Programming on Automata, languages and programming
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Hazard algebras (extended abstract)
A half-century of automata theory
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
More Accurate Polynomial-Time Min-Max Timing Simulation
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Three levels of accuracy for the simulation of different fault types in digital systems
DAC '75 Proceedings of the 12th Design Automation Conference
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Formal Methods in System Design
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Hazards pulses are undesirable short pulses caused by stray delays in digital circuits. Such pulses not only may cause errors in the circuit operation, but also consume energy, and add to the computation time. It is therefore very important to detect hazards in circuit designs. Two-valued Boolean algebra, which is commonly used for the analysis and synthesis of digital circuits, cannot detect hazard conditions directly. To overcome this limitation several multivalued algebras have been proposed for hazard detection. This paper surveys these algebras, and studies their mathematical properties. Also, some recent results unifying most of the multi-valued algebras presented in the literature are described. Our attention in this paper is restricted to the study of static and dynamic hazards in gate circuits.