TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Applications of logic simulation in design automation at Texas Instruments
DAC '72 Proceedings of the 9th Design Automation Workshop
Timing analysis for digital fault simulation using assignable delays
DAC '74 Proceedings of the 11th Design Automation Workshop
Time flow mechanisms for use in digital logic simulation
WSC '71 Proceedings of the 5th conference on Winter simulation
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
An accurate time delay model for large digital network simulation
DAC '76 Proceedings of the 13th Design Automation Conference
Beyond two
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CC-TEGAS3 is a time domain digital logic simulation and test generation system. Presently there are six primary modes of simulation with other modes in development. Modes one through three are for true value simulation only and are used for logic verification and design verification. Modes four through six correspond to modes one through three, respectively, but are for fault simulation. These later modes allow a user to simulate faults at either the logic verification level, (using assignable nominal element propagation delays), or at the design verification level using assignable minimum-maximum delay times. Mode six represents one of the most accurate fault simulators yet to be implemented. The description, analysis, design considerations, implementation techniques, and data structures used in the fault simulation modes of the CC-TEGAS3 system are the subject of this paper.