A three-value computer design verification system

Authors:
J. S. Jephson;R. P. McQuarrie;R. E. Vogelsberg
Affiliations:
-;-;-
Venue:
IBM Systems Journal
Year:
1969

Citing 1
Cited 5

Application of Ternary Algebra to the Study of Static Hazards

Journal of the ACM (JACM)

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Microprogrammed operations for a three-value logic simulator

MICRO 7 Conference record of the 7th annual workshop on Microprogramming
A Note on a Modified Ternary Simulator Capable of Initializing All Fault Machine Memory Elements

IEEE Transactions on Computers
Functional Partitioning and Simulation of Digital Circuits

IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis

IEEE Transactions on Computers

Quantified Score

Hi-index	0.03

Visualization

Abstract

Described is an experimental system for verifying logic designs in the development of a computer before a commitmeat to produce the computer is made. The system simulates logic activity with both known (0, l) and unknown (X) values. The use of the third value facilitates the generation of tests and the detection of circuit hazards.