Exclusive simulation of activity in digital networks
Communications of the ACM
Techniques for the simulation of computer logic
Communications of the ACM
ACM '65 Proceedings of the 1965 20th national conference
High-speed fault simulation for UNIVAC 1107 computer system
ACM '68 Proceedings of the 1968 23rd ACM national conference
IBM Journal of Research and Development
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
A three-value computer design verification system
IBM Systems Journal
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Design for Testability A Survey
IEEE Transactions on Computers
Fault insertion techniques and models for digital logic simulation
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
LSI logic testing: an overview
IEEE Transactions on Computers
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In this paper we present a method for obtaining a functional partitioning of the logic of a computer. It is shown that given a basic function to be performed, such as addition, the computer logic can be partitioned into four disjoint sets, namely the active information logic I, the semiactive flip-flops l, the activated control logic c, and the dormant logic D. Techniques involved in implementing the partitioning algorithm such as an event-directed simulator and three-value simulation are discussed. An application of this partitioning scheme as part of a large logic simulation system is described.