Multigrid solvers in reconfigurable hardware

  • Authors:
  • Safaa J. Kasbah;Issam W. Damaj;Ramzi A. Haraty

  • Affiliations:
  • Division of Computer Science and Mathematics, Lebanese American University, Beirut, Lebanon;Department of Electrical and Computer Engineering, Dhofar University, Salalah, Sultanate of Oman;Division of Computer Science and Mathematics, Lebanese American University, Beirut, Lebanon

  • Venue:
  • Journal of Computational and Applied Mathematics
  • Year:
  • 2008

Quantified Score

Hi-index 7.29

Visualization

Abstract

The problem of finding the solution of partial differential equations (PDEs) plays a central role in modeling real world problems. Over the past years, Multigrid solvers have showed their robustness over other techniques, due to its high convergence rate which is independent of the problem size. For this reason, many attempts for exploiting the inherent parallelism of Multigrid have been made to achieve the desired efficiency and scalability of the method. Yet, most efforts fail in this respect due to many factors (time, resources) governed by software implementations. In this paper, we present a hardware implementation of the V-cycle Multigrid method for finding the solution of a 2D-Poisson equation. We use Handel-C to implement our hardware design, which we map onto available field programmable gate arrays (FPGAs). We analyze the implementation performance using the FPGA vendor's tools. We demonstrate the robustness of Multigrid over other similar iterative solvers, such as Jacobi and successive over relaxation (SOR), in both hardware and software. We compare our findings with a C++ version of each algorithm. The obtained results show better performance when compared to existing software versions.