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Proceedings of the 27th annual international symposium on Computer architecture
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Partitioning Conditional Data Flow Graphs for Embedded System Design
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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Synthesis techniques and optimizations for reconfigurable systems
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IEEE Transactions on Computers
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Exploring the design space of LUT-based transparent accelerators
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Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.