MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the conference on Design, automation and test in Europe
Design space exploration for a coarse grain accelerator
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An architecture framework for an adaptive extensible processor
The Journal of Supercomputing
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
IEICE - Transactions on Information and Systems
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Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an RFU. In this paper, our proposed RFU architecture for an adaptive dynamic extensible processor is described. Then, an integrated framework for temporal partitioning and mapping is presented to partition and map the CIs on RFU. In this framework, two mapping aware temporal partitioning algorithms are used to generate CIs. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. Using this framework brings about more speedup for the extensible processor