Communicating sequential processes
Communicating sequential processes
An introduction to the theory of lists
Proceedings of the NATO Advanced Study Institute on Logic of programming and calculi of discrete design
Solving problems on concurrent processors. Vol. 1: General techniques and regular problems
Solving problems on concurrent processors. Vol. 1: General techniques and regular problems
An introduction to functional programming
An introduction to functional programming
Parallel algorithms for matrix operations and their performance on multiprocessor systems
Advances in parallel algorithms
A comprehensive approach to parallel data flow analysis
ICS '92 Proceedings of the 6th international conference on Supercomputing
Foundations of parallel programming
Foundations of parallel programming
Exploiting parallelism in functional languages: a “paradigm-oriented” approach
Abstract machine models for highly parallel computers
On embedding a microarchitectural design language within Haskell
Proceedings of the fourth ACM SIGPLAN international conference on Functional programming
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Solving Linear Systems on Vector and Shared Memory Computers
Solving Linear Systems on Vector and Shared Memory Computers
Parallel Programming Using Skeleton Functions
PARLE '93 Proceedings of the 5th International PARLE Conference on Parallel Architectures and Languages Europe
Synthesis of Massively Pipelined Algorithms for List Manipulation
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Derivation of Parallel Algorithms from Functional Specifications to CSP Processes
MPC '95 Mathematics of Program Construction
muFP, a language for VLSI design
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
HICSS '03 Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9 - Volume 9
Microprocessor Specification in Hawk
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
Header Compression in Handel-C -- An Internet Application and a New Design Language
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A cellular computer to implement the kalman filter algorithm
A cellular computer to implement the kalman filter algorithm
Algorithmic skeletons: a structured approach to the management of parallel computation
Algorithmic skeletons: a structured approach to the management of parallel computation
Parallel algorithms development for programmable devices with application from cryptography
International Journal of Parallel Programming
Real-time motion detection by lateral inhibition in accumulative computation
Engineering Applications of Artificial Intelligence
Algorithmic lateral inhibition formal model for real-time motion detection
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
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Programmable logic devices (PLDs) continue to grow in size and currently contain several millions of gates. At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can exploit PLD technology. In this paper, we explore the effectiveness and extend one such formal methodology in the design of massively parallel algorithms. We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications. A functional programming notation is used for specifying algorithms and for reasoning about them. The specifications are realised through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The off-the-shelf refinements are inspired by the operators of communicating sequential processes (CSP) and map easily to programs in Handel-C (a hardware description language). The Handel-C descriptions are directly compiled into reconfigurable hardware. The practical realisation of this methodology is evidenced by a case studying the matrix multiplication algorithm as it is relatively simple and well known. In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm. The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.