Communicating sequential processes
Communicating sequential processes
On embedding a microarchitectural design language within Haskell
Proceedings of the fourth ACM SIGPLAN international conference on Functional programming
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Haskell: The Craft of Functional Programming
The Haskell: The Craft of Functional Programming
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Synthesis of Massively Pipelined Algorithms for List Manipulation
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Towards a Provably Correct Hardware Implementation of Occam
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Derivation of Parallel Algorithms from Functional Specifications to CSP Processes
MPC '95 Mathematics of Program Construction
muFP, a language for VLSI design
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
HICSS '03 Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9 - Volume 9
Automatic Model Refinement for Fast Architecture Exploration
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Microprocessor Specification in Hawk
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
Higher-Level Hardware Synthesis
Higher-Level Hardware Synthesis
Parallel algorithms development for programmable logic devices
Advances in Engineering Software
Higher-level hardware synthesis of the KASUMI algorithm
Journal of Computer Science and Technology
| Hi-index | 0.00 |
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), have been witnessing a considerable increase in density. State-of-the-art FPGAs are complex hybrid devices that contain up to several millions of gates. Recently, research effort has been going into higher-level parallelization and hardware synthesis methodologies that can exploit such a programmane technology. In this paper, we explore the effectiveness of one such formal methodology in the design of parallel versions of the Serpent cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The specifications are realized through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The refinements are inspired by the operators of Communicating Sequential Processes and map easily to programs in Handel-C (a hardware description language). In the presented research, we obtain several parallel Serpent implementations with different performance characteristics. The developed designs are tested under Celoxica's RC-1000 reconfigurable computer with its two million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.