Formal Behavioural Synthesis of Handel-C Parallel Hardware Implementations from Functional Specifications

  • Authors:
  • Ali E. Abdallah;John Hawkins

  • Affiliations:
  • -;-

  • Venue:
  • HICSS '03 Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9 - Volume 9
  • Year:
  • 2003

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Abstract

Enormous improvements in efficiency can beachieved through exploiting parallelism and realizingimplementation in hardware. On the other hand, conventional methods for achieving these improvementsare traditionally costly, complex and error prone. Twosignifficant advances in the past decade have radicallychanged these perceptions. Firstly, the FPGA, whichgives us the ability to reconfigure hardware throughsoftware, dramatically reducing the costs of developing hardware implementations. Secondly, the languageHandel-C with primitive explicit parallelism which cancompile programs down to an FPGA. In this paper, webuild on these recent technological advances and presenta systematic approach of behavioural synthesis. Starting with an intuitive high level functional specificationof a problem, given without annotation of parallelism, the approach aims at deriving an efficient parallel implementation in Handel-C, which is subsequently compiled into a circuit implemented on reconfigurable hardware. Algebraic laws are systematically used for exposing implicit parallelism and transforming the specification into a collection of interacting components. Formal methods based on data refinement and a small library of higher order functions are then used to derive behavioural description in Handel-C of each component. A small case study illustrates the use of thisapproach.