Communicating sequential processes
Communicating sequential processes
Synthesis of Massively Pipelined Algorithms for List Manipulation
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms
ISC '01 Proceedings of the 4th International Conference on Information Security
Derivation of Parallel Algorithms from Functional Specifications to CSP Processes
MPC '95 Mathematics of Program Construction
HICSS '03 Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9 - Volume 9
A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions
Proceedings of the 15th symposium on Integrated circuits and systems design
Automatic Model Refinement for Fast Architecture Exploration
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Higher-level hardware synthesis of the KASUMI algorithm
Journal of Computer Science and Technology
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Recently, hardware designers have been showing considerable attention to high-level parallelization and hardware synthesis methodologies. State-of-the-art approaches has benefited from the emergence of modern high-density Field-programmable Gate Arrays (FPGAs). In this paper, we explore the effectiveness of a formal methodology in the design of parallel versions of the F8 cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The parallel behavior of the specification is then derived and mapped onto hardware. Several parallel F8 implementations are developed with different performance characteristics. The refined designs are tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of the proposed implementations are included.