A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions

Authors:
João M. S. Alcântara;Antônio C. C. Vieira;Federico Gálvez- Durand;Vladimir Castro Alves
Affiliations:
-;-;-;-
Venue:
Proceedings of the 15th symposium on Integrated circuits and systems design
Year:
2002

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Abstract

Power consumption became an important feature to be considered in system implementations. This work presents a methodology for dynamic power consumption estimation using hardware descriptions written in VHDL; a library with information for transitions and power consumption for all components of the target library is created. A case study for the KASUMI cryptographicalgorithm is reported. This algorithm was chosen to compose The 3rd Generation Partnership Project (3GPP) security functions for mobile systems. Restrictions imposed by the 3GPP to the hardware implementation of KASUMI cryptographic algorithm were analyzed and satisfied; our dynamic power consumption estimation methodology is used. Only CMOS technologies arediscussed in this paper.