Performance of reconfigurable architectures for image-processing applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Parallel algorithms development for programmable logic devices
Advances in Engineering Software
Design and implementation of JPEG2000 arithmetic decoder based on Handel-C
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
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Abstract: In the ESPRIT project "Software engineering for Hardware Design", a critical and complex function in the Ericsson IPv6 router RXI820 was designed. The router is optimized for voice transmission in the mobile base station network. IP Header Compression (RFC 2507), compresses and restores long headers of packets in point-to- point message streams improving bandwidth utilization and real-time characteristics. The function was implemented in FPGA technology using a new high-level design language based on the software language ANSI-C. The design method used is similar to methods for software design. The resulting hardware can be tested in full speed on a PCI-board. In a parallel effort, a second group of designers using the same specification implemented the same functionality using traditional hardware design methods and tools. This enabled us to compare the efficiency of the two design methods. Using the new methods, the design was completed 3-4 times faster with similar results in terms of speed and area. This can be attributed to support for sequential logic and a compact representation in the language and to a software-like design methodology with fast turnaround in the design environment.