Hierarchical loop partitioning for rapid generation of runtime configurations

Authors:
Siew-Kei Lam;Yun Deng;Jian Hu;Xilong Zhou;Thambipillai Srikanthan
Affiliations:
Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;School of Software and Microelectronics, Peking University, P.R. China;School of Software and Microelectronics, Peking University, P.R. China;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore
Venue:
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Year:
2010

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Abstract

Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying the performance, flexibility and power requirements of embedded systems. The growing complexity of the applications necessitates methods that can rapidly identify a suitable set of configurations by splitting the computational structures into temporal partitions in order to evaluate the benefits of runtime reconfiguration early in the design cycle. In this paper, we present a hierarchical loop partitioning strategy that reduces the complexity of the search space for determining the runtime custom instruction configurations for reconfigurable processors. Experimental results show that the proposed partitioning strategy can lead to an average and maximum performance gain (in terms of clock cycle savings) of over 14% and 31% respectively when compared to a recently reported technique. In addition, when compared to the existing technique, the proposed partitioning method has significantly lower runtime in many of the cases considered.