High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Communications of the ACM
Wisconsin Architectural Research Tool Set
ACM SIGARCH Computer Architecture News
Optimally profiling and tracing programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Specification and design of embedded systems
Specification and design of embedded systems
Decompilation: the enumeration of types and grammars
ACM Transactions on Programming Languages and Systems (TOPLAS)
EEL: machine-independent executable editing
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Exploiting hardware performance counters with flow and context sensitive profiling
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Java as a specification language for hardware-software systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Customized instruction-sets for embedded processors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Description and simulation of hardware/software systems with Java
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Software profiling for hot path prediction: less is more
ACM SIGPLAN Notices
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
SystemC: a homogenous environment to test embedded systems
Proceedings of the ninth international symposium on Hardware/software codesign
Dynamic Binary Translation and Optimization
IEEE Transactions on Computers
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
FX!32: A Profile-Directed Binary Translator
IEEE Micro
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A systems implementation language for small computers
Proceeding of ACM SIGPLAN - SIGOPS interface meeting on Programming languages - operating systems
A methodology for machine language decompilation
ACM '74 Proceedings of the 1974 annual conference - Volume 1
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Comparing Type-Based and Proof-Directed Decompilation
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
Computer Security Analysis through Decompilation and High-Level Debugging
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
Designing the M·CORETM M3 CPU Architecture
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Decompilation of object programs
Decompilation of object programs
Decompilation.
Frequent loop detection using efficient non-intrusive on-chip hardware
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Advanced obfuscation techniques for Java bytecode
Journal of Systems and Software
Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
Dynamic FPGA routing for just-in-time FPGA compilation
Proceedings of the 41st annual Design Automation Conference
Input data reuse in compiling window operations onto reconfigurable hardware
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Techniques for synthesizing binaries to an advanced register/memory structure
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Programmable Hardware Path Profiler
Proceedings of the international symposium on Code generation and optimization
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 42nd annual Design Automation Conference
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Hardware/software partitioning of software binaries: a case study of H.264 decode
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
New decompilation techniques for binary-level co-processor generation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 41st annual Design Automation Conference
Instrumentation and optimization of Win32/intel executables using Etch
NT'97 Proceedings of the USENIX Windows NT Workshop on The USENIX Windows NT Workshop 1997
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Concept-based partitioning for large multidomain multifunctional embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
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Recent high-level synthesis approaches and C-based hardware description languages attempt to improve the hardware design process by allowing developers to capture desired hardware functionality in a well-known high-level source language. However, these approaches have yet to achieve wide commercial success due in part to the difficulty of incorporating such approaches into software tool flows. The requirement of using a specific language, compiler, or development environment may cause many software developers to resist such approaches due to the difficulty and possible instability of changing well-established robust tool flows. Thus, in the past several years, synthesis from binaries has been introduced, both in research and in commercial tools, as a means of better integrating with tool flows by supporting all high-level languages and software compilers. Binary synthesis can be more easily integrated into a software development tool-flow by only requiring an additional backend tool, and it even enables completely transparent dynamic translation of executing binaries to configurable hardware circuits. In this article, we survey the key technologies underlying the important emerging field of binary synthesis. We compare binary synthesis to several related areas of research, and we then describe the key technologies required for effective binary synthesis: decompilation techniques necessary for binary synthesis to achieve results competitive with source-level synthesis, hardware/software partitioning methods necessary to find critical binary regions suitable for synthesis, synthesis methods for converting regions to custom circuits, and binary update methods that enable replacement of critical binary regions by circuits.