Techniques for synthesizing binaries to an advanced register/memory structure

  • Authors:

  • Greg Stitt;Zhi Guo;Walid Najjar;Frank Vahid

  • Affiliations:

  • University of California, Riverside, CA;University of California, Riverside, CA;University of California, Riverside, CA;University of California, Riverside, CA and University of California, Irvine, CA

  • Venue:
  • Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
  • Year:
  • 2005

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Abstract

Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with minimal impact, porting existing binaries to FPGAs, and even dynamically synthesizing software kernels to faster FPGA coprocessors. Those works showed that standard binary decompilation methods can recover enough high-level control information to result in reasonably-efficient hardware. However, recent synthesis methods for FPGAs utilize advanced memory structures, such as a "smart buffer," that require recovery of additional high-level information, specifically information about loops and arrays. We incorporate decompilation techniques into an existing binary synthesis tool flow to recover loops and arrays in order to take advantage of advanced memory structures when performing synthesis from a binary. We demonstrate through experiments on six benchmarks that our methods improve binary synthesis performance by 53%, by making effective use of smart buffers. Furthermore, we compare the binary results using smart buffers with results of synthesis directly from the original C code for the benchmarks, and show that our methods achieved almost identical performance results with only 10% area overhead.