Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Execution-Based Scheduling for VLIW Architectures
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Relational profiling: enabling thread-level parallelism in virtual machines
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Performance characterization of a hardware mechanism for dynamic optimization
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Precise Exception Semantics in Dynamic Compilation
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Dynamic binary translation for accumulator-oriented architectures
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Dynamic trace selection using performance monitoring hardware sampling
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Continuous program optimization: A case study
ACM Transactions on Programming Languages and Systems (TOPLAS)
Selecting long atomic traces for high coverage
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Optimization of Micro-Operations
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A brief history of just-in-time
ACM Computing Surveys (CSUR)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
Dynamic FPGA routing for just-in-time FPGA compilation
Proceedings of the 41st annual Design Automation Conference
Power Awareness through Selective Dynamically Optimized Traces
Proceedings of the 31st annual international symposium on Computer architecture
Automatic Synthesis of High-Speed Processor Simulators
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Application of Binary Translation to Java Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Proceedings of the 42nd annual Design Automation Conference
Exploiting Java through binary translation for low power embedded reconfigurable systems
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Improving Region Selection in Dynamic Optimization Systems
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Automatic extraction of function bodies from software binaries
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Constructing Virtual Architectures on a Tiled Processor
Proceedings of the International Symposium on Code Generation and Optimization
Metadata driven memory optimizations in dynamic binary translator
Proceedings of the 3rd international conference on Virtual execution environments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An overview of a compiler for mapping software binaries to hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transparent reconfigurable acceleration for heterogeneous embedded applications
Proceedings of the conference on Design, automation and test in Europe
Exploiting an abstract-machine-based framework in the design of a Java ILP processor
Journal of Systems Architecture: the EUROMICRO Journal
MobiVMM: a virtual machine monitor for mobile phones
Proceedings of the First Workshop on Virtualization in Mobile Computing
Efficient binary translation system with low hardware cost
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
DisIRer: Converting a retargetable compiler into a multiplatform binary translator
ACM Transactions on Architecture and Code Optimization (TACO)
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Evaluating indirect branch handling mechanisms in software dynamic translation systems
ACM Transactions on Architecture and Code Optimization (TACO)
Towards an adaptable multiple-ISA reconfigurable processor
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
PARROT: power awareness through selective dynamically optimized traces
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Background optimization in full system binary translation
Programming and Computing Software
LLBT: an LLVM-based static binary translator
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Towards a multiple-ISA embedded system
Journal of Systems Architecture: the EUROMICRO Journal
Exploiting binary translation for fast ASIP design space exploration on fpgas
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 4.10 |
High-frequency design and instruction-level parallelism (ILP) are important for high-performance microprocessor implementations. The Binary-translation Optimized Architecture (BOA), an implementation of the IBM PowerPC family, combines binary translation with dynamic optimization. The authors use these techniques to simplify the hardware by bridging a semantic gap between the PowerPC's reduced instruction set and even simpler hardware primitives.Processors like the Pentium Pro and Power4 have tried to achieve high frequency and ILP by implementing a cracking scheme in hardware: An instruction decoder in the pipeline generates multiple micro-operations that can then be scheduled out of order. BOA relies on an alternative software approach to decompose complex operations and to generate schedules, and thus offers significant advantages over purely static compilation approaches. This article explains BOA's translation strategy, detailing system issues and architecture implementation.