Communications of the ACM
DIGITAL FX!32: combining emulation and binary translation
Digital Technical Journal
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
FX!32: A Profile-Directed Binary Translator
IEEE Micro
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd annual Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Transparent reconfigurable acceleration for heterogeneous embedded applications
Proceedings of the conference on Design, automation and test in Europe
Dynamically Adapted Low Power ASIPs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Limits of parallelism using dynamic dependency graphs
WODA '09 Proceedings of the Seventh International Workshop on Dynamic Analysis
| Hi-index | 0.00 |
As technology advances, new hardware approaches are proposed to speed up software execution. However, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. As binary translation allows the execution of binary codes of already compiled applications on different architectures, it opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues. The problem with binary translation is its inherent performance penalty: it will always take more cycles than the simple execution on the native machine. To address that, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto (in our first implemented case study, X86 to MIPS translations), the second level optimizes the already translated instructions to be executed on a dynamically adaptable reconfigurable architecture. This way, both software portability and performance are maintained.