Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
rePLay: A Hardware Framework for Dynamic Optimization
IEEE Transactions on Computers
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Design space exploration of partially re-configurable embedded processors
Proceedings of the conference on Design, automation and test in Europe
Transparent reconfigurable acceleration for heterogeneous embedded applications
Proceedings of the conference on Design, automation and test in Europe
European research in embedded systems
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Towards an adaptable multiple-ISA reconfigurable processor
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
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New generations of embedded devices, following the trend found in personal computers, are becoming computationally powerful. A current embedded scenario presents a large amount of complex and heterogeneous functionalities, which have been forcing designers to create novel solutions to increase the performance of embedded processors while, at the same time, maintain power dissipation as low as possible. Former embedded devices could have been designed to execute a defined application set. Nowadays, in the new generation of these devices, some applications are unknown at design time. For example, in portable phones, the client is able to download new applications during the product lifetime. Hence, traditional designs can fail to deliver the required performance while executing an application behavior that has not been previously defined. On the other hand, reconfigurable architectures appear to be a possible solution to increase the processor performance, but their employment in embedded devices faces two main design constraints: power and area. In this work, we propose an ASIP reconfigurable development flow that aggregates design area optimization and a run-time technique that reduces energy consumption. The coupling of both methods builds an area optimized reconfigurable architecture to provide a high-performance and energy-efficient execution of a defined application set. Moreover, thanks to the adaptability provided by the reconfigurable ASIP approach, the execution of new application not foreseen at design time still shows high speedups rates with low energy consumption.