Boosting parallel applications performance on applying DIM technique in a multiprocessing environment

  • Authors:

  • Mateus B. Rutzig;Antonio C. S. Beck;Felipe Madruga;Marco A. Alves;Henrique C. Freitas;Nicolas Maillard;Philippe O. A. Navaux;Luigi Carro

  • Affiliations:

  • Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, MG, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil

  • Venue:
  • International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
  • Year:
  • 2011

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Abstract

Limits of instruction-level parallelism and higher transistor density sustain the increasing need formultiprocessor systems: they are rapidly taking over both general-purpose and embedded processor domains. Current multiprocessing systems are composed either of many homogeneous and simple cores or of complex superscalar, simultaneous multithread processing elements. As parallel applications are becoming increasingly present in embedded and general-purpose domains and multiprocessing systems must handle a wide range of different application classes, there is no consensus over which are the best hardware solutions to better exploit instruction-level parallelism (TLP) and thread-level parallelism (TLP) together. Therefore, in this work, we have expanded the DIM (dynamic instruction merging) technique to be used in a multiprocessing scenario, proving the need for an adaptable ILP exploitation even in TLP architectures. We have successfully coupled a dynamic reconfigurable system to an SPARC-based multiprocessor and obtained performance gains of up to 40%, even for applications that show a great level of parallelism at thread level.