Exploiting Java through binary translation for low power embedded reconfigurable systems

Authors:
Antonio Carlos S. Beck;Victor F. Gomes;Luigi Carro
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil
Venue:
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Year:
2005

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Abstract

In this paper we present a Binary Translation algorithm to detect, completely at run-time, sequences of instructions to be executed in a reconfigurable array, which in turn is coupled to an embedded Java processor. By translating any sequence of operations into a combinational circuit performing the same computation, one can speed up the system and reduce energy consumption, at the obvious price of extra area. We show what are the costs to implement this translation algorithm in hardware, and what are the performance and energy gains when using such technique. Furthermore, we demonstrate that this translation algorithm is particularly easy to be implemented in a stack machine, because of its particular computational method. Algorithms used in the embedded systems domain were accelerated 4.6 times in the mean, while spending almost 11 times less energy.