Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Introduction to algorithms
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Forward-looking objective functions: concept & applications in high level synthesis
Proceedings of the 39th annual Design Automation Conference
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A system for synthesizing optimized FPGA hardware from MATLAB
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Cameron: High Level Language Compilation for Reconfigurable Systems
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
System synthesis using behavioural descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
Achieving Design Closure Through Delay Relaxation Parameter
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Quick Reconfiguration in Clustered Micro-Sequencer
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Area optimization of multi-cycle operators in high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Max-Flow Scheduling in High-Level Synthesis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration
International Journal of Applied Mathematics and Computer Science
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Complexities of applications implemented on embedded and programmable systems grow with the advances in capacities and capabilities of these systems. Mapping applications onto them manually is becoming a very tedious task. This draws attention to using high-level synthesis within design flows. Meanwhile, it is essential to provide a flexible formulation of optimization objectives as well as to perform efficient planning for various design objectives early on in the design flow. In this work, we address these issues in the context of data flow graph (DFG) scheduling, which is an essential element within the high-level synthesis flow. We present an algorithm that schedules a chain of operations with data dependencies among consecutive operations at a single step. This local problem is repeated to generate the schedule for the whole DFG. The local problem is formulated as a maximum weight noncrossing bipartite matching. We use a technique from the computational geometry domain to solve the matching problem. This technique provides a theoretical guarantee on the solution quality for scheduling a single chain of operations. Although still being local, this provides a relatively wider perspective on the global scheduling objectives. In our experiments we compared the latencies obtained using our algorithm with the optimal latencies given by the exact solution to the integer linear programming (ILP) formulation of the problem. In 9 out of 14 DFGs tested, our algorithm found the optimal solution, while generating latencies comparable to the optimal solution in the remaining five benchmarks. The formulation of the objective function in our algorithm provides flexibility to incorporate different optimization goals. We present examples of how to exploit the versatility of our algorithm with specific examples of objective functions and experimental results on the ability of our algorithm to capture these objectives efficiently in the final schedules.