The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
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Current design automation methodologies are becoming incapableof achieving design closure especially in the presence of deep submicroneffects. This paper addresses the issue of design closure from ahigh level point of view. A new metric called delay relaxation parameter(DRP) for RTL (Register Transfer Level) designs is proposed. DRPessentially captures the degree of delay relaxation that the design cantolerate without violating the clock constraint. This metric when optimizedresults in quicker design flow. Algorithms to optimize DRP areformulated and their optimality are investigated. Experimental resultsare conducted using a state of the art design flow with Synopsys DesignCompiler followed by Cadence Place and Route. Our approachof optimizing DRP resulted in lesser design iterations and faster designclosure as compared to designs generated through Synopsys BehavioralCompiler and a representative academic design flow.