Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
A new algorithm for the maximum-weight clique problem
Nordic Journal of Computing
Global resource sharing for synthesis of control data flow graphs on FPGAs
Proceedings of the 40th annual Design Automation Conference
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Journal of Experimental Algorithmics (JEA)
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
A modified merging approach for datapath configuration time reduction
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Reconfigurable systems have been proved to achieve significant performance speed-up by mapping the most time-consuming loops to a reconfigurable units. Datapath merging (DPM) synthesis has identified the similarities among the Data Flow Graphs (DFGs) corresponding to the loops, and produces a single reconfigurable datapath that can be dynamically reconfigured to execute each DFG. This paper presents a new datapath merging method that produces a reconfigurable datapath with minimal area usage. At first it merges DFGs together one by one to create the reconfigurable datapath. Then it merges the functional units and interconnection units inside the reconfigurable datapath to reduce resource area usage. To do this, a new graph-based technique to merge the resources in the reconfigurable datapath is presented. We evaluate the proposed method using programs from the Media-bench benchmarks and experimental results show a decrease from 5% to 15% in reconfigurable data path resource area in comparison to previous algorithms.