Efficient sequential and parallel algorithms for maximal bipartite sets
Journal of Algorithms
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the conference on Design, automation and test in Europe
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters
EDTC '96 Proceedings of the 1996 European conference on Design and Test
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Graph clustering using the weighted minimum common supergraph
GbRPR'03 Proceedings of the 4th IAPR international conference on Graph based representations in pattern recognition
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Journal of Experimental Algorithmics (JEA)
Automatic application specific floating-point unit generation
Proceedings of the conference on Design, automation and test in Europe
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
Rapid application specific floating-point unit generation with bit-alignment
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Beam search for the longest common subsequence problem
Computers and Operations Research
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-space exploration of resource-sharing solutions for custom instruction set extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A hybrid metaheuristic for the longest common subsequence problem
HM'10 Proceedings of the 7th international conference on Hybrid metaheuristics
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An improved algorithm for the longest common subsequence problem
Computers and Operations Research
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
A hyper-heuristic for the Longest Common Subsequence problem
Computational Biology and Chemistry
Instruction set architectural guidelines for embedded packet-processing engines
Journal of Systems Architecture: the EUROMICRO Journal
Placing multimode streaming applications on dynamically partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture support for custom instructions with memory operations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Resource-constrained high-level datapath optimization in ASIP design
Proceedings of the Conference on Design, Automation and Test in Europe
Predicting best design trade-offs: a case study in processor customization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Selective flexibility: breaking the rigidity of datapath merging
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Architecture customization of on-chip reconfigurable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
Hi-index | 0.00 |
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these compilers produce hardware that is larger than necessary, as they do not allow instructions to share hardware resources. This study presents an efficient heuristic which transforms a set of custom instructions into a single hardware datapath on which they can execute. Our approach is based on the classic problems of finding the longest common subsequence and substring of two (or more) sequences. This heuristic produces circuits which are as much as 85.33% smaller than those synthesized by integer linear programming (ILP) approaches which do not explore resource sharing. On average, we obtained 55.41% area reduction for pipelined datapaths, and 66.92% area reduction for VLIW datapaths. Our solution is simple and effective, and can easily be integrated into an existing silicon compiler.