A high-level synthesis flow for custom instruction set extensions for application-specific processors

Authors:
Nagaraju Pothineni;Philip Brisk;Paolo Ienne;Anshul Kumar;Kolin Paul
Affiliations:
Google India Pvt Ltd., Bangalore, India;University of California, Riverside, Riverside, CA;Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland, CH;Indian Institute of Technology, Delhi, New Delhi, India;Indian Institute of Technology, Delhi, New Delhi, India
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

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Abstract

Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality.