Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling in Computer and Manufacturing Systems
Scheduling in Computer and Manufacturing Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and Engineering Computation)
Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and Engineering Computation)
An Introduction to High-Level Synthesis
IEEE Design & Test
High-Level Synthesis: Past, Present, and Future
IEEE Design & Test
A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Estimating architectural resources and performance for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach to the scheduling problem in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global optimization approach for architectural synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lower-bound performance estimation for the high-level synthesis scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As a key step of high-level synthesis (HLS), resource constrained scheduling (RCS) tries to find an optimal schedule which can dispatch all the operations with minimum latency under specific resource constraints. Branch-and-bound heuristics are promising to achieve such an optimal schedule quickly, since they can prune away large parts of infeasible solution space during the exploration. However, few of them are based on the prevalent multi-core platforms. Based on the bound information, this paper exploits the parallel pruning potentials from different perspectives and proposes various efficient techniques that can substantially reduce the overall RCS search efforts. The experimental results demonstrate that our approach can reduce the RCS time drastically.