Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Today's customizable processors allow the designer to aug- ment the base processor with custom accelerators. By choos- ing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the optimal combination of accelerators is quite cumbersome and time consuming. This calls for CAD tools that select optimal combination of accelerators by thoroughly searching the entire design space. The term pattern is commonly used to represent the computation performed by a custom acceler- ator. In this paper, we propose an algorithm for rapidly enu- merating all the legal patterns taking into account several constraints posed by a typical micro-architecture. The pro- posed algorithm achieves significant reduction in run-time by a) enumerating the patterns in the increasing order of sizes and b) relating the characteristics of a (k + 1) node pattern with the characteristics of its k node subgraphs. Also, in scenarios where I/O is not a bottleneck, designer can optionally relax the I/O constraint and our algorithm efficiently enumerates all legal I/O unbound legal patterns. The experimental evidence indicate an order of two run-time speedup over state of the art techniques.