Architecture support for custom instructions with memory operations

Authors:
Jason Cong;Karthik Gururaj
Affiliations:
University of California Los Angeles, Los Angeles, CA, USA;University of California Los Angeles, Los Angeles, CA, USA
Venue:
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2013

Citing 14
Cited 0

CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit

Proceedings of the 27th annual international symposium on Computer architecture
The effect of reconfigurable units in superscalar processors

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Garp: a MIPS processor with a reconfigurable coprocessor

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Application-specific instruction generation for configurable processor architectures

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs

Proceedings of the 41st annual Design Automation Conference
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Efficient ASIP design for configurable processors with fine-grained resource sharing

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
VEAL: Virtualized Execution Accelerator for Loops

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Virtual ways: efficient coherence for architecturally visible storage in automatic instruction set extensions

HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Introduction of Architecturally Visible Storage in Instruction Set Extensions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CHIPS: Custom Hardware Instruction Processor Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Customized instructions (CIs) implemented using custom functional units (CFUs) have been proposed as a way of improving performance and energy efficiency of software while minimizing cost of designing and verifying accelerators from scratch. However, previous work allows CIs to only communicate with the processor through registers or with limited memory operations. In this work we propose an architecture that allows CIs to seamlessly execute memory operations without any special synchronization operations to guarantee program order of instructions. Our results show that our architecture can provide 24\% energy savings with 14% performance improvement for 2-issue and 4-issue superscalar processor cores.