Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
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VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
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Self-organizing computer vision for robust object tracking in smart cameras
ATC'10 Proceedings of the 7th international conference on Autonomic and trusted computing
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FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Symbolic design space exploration for multi-mode reconfigurable systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in differentmodes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.