Efficient Reconfigurable On-Chip Buses for FPGAs

Authors:
Dirk Koch;Christian Haubelt;Jürgen Teich
Affiliations:
-;-;-
Venue:
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Year:
2008

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Abstract

This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.