IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Recent Developments in Configurable and Extensible Processors
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Custom Instruction Generation with High-Level Synthesis
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Protective redundancy overhead reduction using instruction vulnerability factor
Proceedings of the 7th ACM international conference on Computing frontiers
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model
IEEE Transactions on Dependable and Secure Computing
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs
IEEE Transactions on Computers
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FISH: Fast Instruction SyntHesis for Custom Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic
RTCSA '12 Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Vulnerability Analysis for Custom Instructions
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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Random variations and low reliability of nanometer new silicons are the most important concerns for the fault-tolerant design of large-area powerful integrated circuits. Logic faults in terms of soft errors or transient faults are now serious problems for embedded processing cores. Recently, augmenting an embedded processor with application specific custom instructions is widely used for improving the performance of a processor. Although area, power, and performance of an augmented processor have been considered for efficient custom instruction selection, its reliability consideration is much needed. This is impeding because this action needs exhaustive fault injection and lengthy and expensive simulations. This demand becomes more serious in the case of many-core, larger area and, therefore, more fault-prone integrated circuits, e.g., tera-computing processors. In this work, we propose an analytical modeling solution for such a demanding problem. First, a simple analytical method is introduced that can evaluate the vulnerability of a custom instruction in a time-saving manner. Using this method and our configurable custom instruction vulnerability analysis framework, the effects of type, order, and word length of various operations of different custom instruction subgraphs on the vulnerability of an extensible processor have been explored analytically and experimentally. Based on our results, for example, replacing orders of operators in custom functional units could yield different vulnerabilities to soft errors. Therefore, our approach enables designers to optionally constrain the operand types and also the custom functional unit structures to reach an acceptable vulnerability level at low computational and design time costs.