PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
A C/C++ Source-to-Source Compiler for Dependable Applications
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Instruction Scheduling for Low Power
Journal of VLSI Signal Processing Systems
Compiler-Directed Instruction Duplication for Soft Error Detection
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Compiler-guided register reliability improvement against soft errors
Proceedings of the 5th ACM international conference on Embedded software
Software-controlled fault tolerance
ACM Transactions on Architecture and Code Optimization (TACO)
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
The Instruction Scheduling for Soft Errors Based on Data Flow Analysis
PRDC '09 Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing
Journal of Signal Processing Systems
Multicore soft error rate stabilization using adaptive dual modular redundancy
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
Proceedings of the Conference on Design, Automation and Test in Europe
Low cost permanent fault detection using ultra-reduced instruction set co-processors
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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An instruction scheduling technique is presented that targets at improving the reliability of a software program given a user-provided tolerable performance overhead. A look-ahead-based heuristic schedules instructions by evaluating the reliability of dependent instructions while reducing the impact of spatial and temporal vulnerabilities of various processor components. Our reliability-driven instruction scheduler (implemented into the GCC compiler) provides on average a 22% reduction of program failures compared to state-of-the-art.