Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
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Soft errors are emerging as a new challenge in computer applications. To mitigate the effects of soft errors, a variety of techniques have been proposed in the past. They can be mainly classified into two types: hardware-based and software-based. Hardware-based methods are expensive, since they require replicated hardware modules or developing custom hardware equipment. Although software-based methods do not incur the high economical costs, they usually utilize the strategies of data duplication and time redundancy for tolerating soft errors, which provoke memory overhead and performance degradation. In this paper, we propose a compiler optimization approach that can enhance the reliability of programs without extra costs. The basic idea is to use instruction scheduling to decrease the total valid area that is vulnerable to soft errors during the execution process. Based on the result of data flow analysis, the concrete algorithm for basic block scheduling is described in the dynamic programming fashion. The experimental results of fault injection indicate that the average reliability of the benchmark programs have been improved for 2% without palpable overhead.