Asymmetrically banked value-aware register files for low-energy and high-performance
Microprocessors & Microsystems
Techniques for Efficient Software Checking
Languages and Compilers for Parallel Computing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reducing parity generation latency through input value aware circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Proceedings of the Conference on Design, Automation and Test in Europe
A framework for correction of multi-bit soft errors in L2 caches based on redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft errors induced by high-energy particle strikes. Since the register file is in the critical path of the processor pipeline, any reliable design that increases either the pressure on the register file or the register file access latency is not desirable. In this paper, we propose to exploit narrow-width register values, which present the majority of the generated values, for duplicating a copy of the value within the same data item, called in-register duplication (IRD), eliminating the requirement of additional copy registers. The datapath pipeline is augmented to efficiently incorporate parity encoding and parity checking such that error recovery is seamlessly supported in IRD and the parity checking is overlapped with the execution stage to avoid increasing the critical path. Our experimental evaluation using the SPEC CINT2000 benchmark suite shows that IRD provides superior read-with-duplicate (RWD) and error detection/ recovery rates under heavy error injection as compared to previous reliability schemes.