Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Proceedings of the 39th annual Design Automation Conference
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Architecture generation of customized reconfigurable hardware
Architecture generation of customized reconfigurable hardware
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Totem: Custom Reconfigurable Array Generation
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Place and route techniques for fpga architecture advancement
Place and route techniques for fpga architecture advancement
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
System architecture and implementation of MIMO sphere decoders on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Application-Specific FPGA using heterogeneous logic blocks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Application specific FPGA using heterogeneous logic blocks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Microprocessors & Microsystems
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
| Hi-index | 14.98 |
Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case and miss optimization opportunities present if characteristics of the desired application set are known. Restricting the structure to support a class or a specific set of algorithms can increase efficiency while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. This paper discusses configurable ASIC (cASIC) architecture generation that creates hardware on average up to 12.3x smaller than an FPGA solution with embedded multipliers and 2.2x smaller than a standard cell implementation of individual circuits.