Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Area optimization of multi-functional processing units
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Quadratic zero-one programming based synthesis of application specific data paths
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Bit-Width Selection for Data-Path Implementations
Proceedings of the 12th international symposium on System synthesis
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Experimental Algorithmics (JEA)
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
EURASIP Journal on Applied Signal Processing
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Special Issue on High-Level Synthesis
IEEE Design & Test
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Path-based scheduling for synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms provided by FPGA devices offer partial reconfiguration at runtime. However they require too long reconfiguration times and they cannot satisfy mobile device power consumption requirements. In this article we propose a methodology to map selected groups of DSP tasks to multi-mode cores using conventional hardware technologies.