Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Bit-Width Selection for Data-Path Implementations
Proceedings of the 12th international symposium on System synthesis
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Optimizing Register Binding in FPGAs Using Simulated Annealing
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Bitwidth-aware scheduling and binding in high-level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pattern-based behavior synthesis for FPGA resource reduction
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
Impact of FPGA architecture on resource sharing in high-level synthesis
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
| Hi-index | 0.00 |
High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. While such tools were developed targeting ASIC technologies, HLS currently draws wide interest for FPGA designers. However with most of HLS techniques, traditional resource sharing models are very inaccurate for FPGAs: for example, multiplexers can be very expensive with such technologies. Resource usage optimizations and dedicated resource binding have to be applied. In this paper a HLS process which takes care of data-width and combines scheduling and binding to carefully take into account interconnect cost is presented. Experimental results show that our approach achieves significant reduction for area (34%) and dynamic power (28%) compared to a traditional synthesis.