Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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When variables are assigned to registers or memories in FPGAs, multiplexers are needed for correct operation of the design. These multiplexers are needed at the input registers or memories if different functional units are writing to the same storage unit. Since in FPGAs the area covered by multiplexers is significantly large compared with the area of the overall design, reducing the area of the multiplexers can reduce the overall area occupied by a design. Reducing the area of a design is essential to efficiently utilize the logic area of the FPGAs. This paper proposes a solution that applies simulated annealing after binding variables to storage elements. This solution optimizes the assignment of variables onto registers when standard techniques such as clique partitioning are used; and onto on-chip memory banks when two different memory binding techniques are used. The savings obtained in terms of multiplexer area reaches 27% with an average of 16%; moreover, the overall logic area savings reaches 17% with an average of 7%.