IEEE Transactions on Computers
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Coarse grain reconfigurable architecture (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Global resource sharing for synthesis of control data flow graphs on FPGAs
Proceedings of the 40th annual Design Automation Conference
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reconfigurable Coprocessor for Multimedia Application Domain
Journal of VLSI Signal Processing Systems
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software Code Generation for the RVC-CAL Language
Journal of Signal Processing Systems
Synthesizing Hardware from Dataflow Programs
Journal of Signal Processing Systems
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures
IEEE Embedded Systems Letters
Hi-index | 0.00 |
Dataflow specifications are suitable to describe both signal processing applications and the relative specialized hardware architectures, fostering the hardware---software development gap closure. They can be exploited for the development of automatic tools aimed at the integration of multiple applications on the same coarse-grained computational substrate. In this paper, the multi-dataflow composer (MDC) tool, a novel automatic platform builder exploiting dataflow specifications for the creation of run-time reconfigurable multi-application systems, is presented and evaluated. In order to prove the effectiveness of the adopted approach, a coprocessor for still image and video processing acceleration has been assembled and implemented on both FPGA and 90 nm ASIC technology. 60 % of savings for both area occupancy and power consumption can be achieved with the MDC generated coprocessor compared to an equivalent non-reconfigurable design, without performance losses. Thanks to the generality of high-level dataflow specification approach, this tool can be successfully applied in different application domains.