A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
IEEE Transactions on Computers
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Interconnection Networks for Multiprocessors and Multicomputers: Theory and Practice
Interconnection Networks for Multiprocessors and Multicomputers: Theory and Practice
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Augmenting a microprocessor with reconfigurable hardware
Augmenting a microprocessor with reconfigurable hardware
Reconfigurable Operator Based Multimedia Embedded Processor
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
Journal of Real-Time Image Processing
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A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized) for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has been synthesized using Synopsys Design Compiler on a standard-cell 0.18 驴 m technology. Estimated number of transistors is 335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to 95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles.