Timing and Design Closure in Physical Design Flows

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ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Year:
2002

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Abstract

A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. This paper focuses on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.