Heuristics: intelligent search strategies for computer problem solving
Heuristics: intelligent search strategies for computer problem solving
Fibonacci heaps and their uses in improved network optimization algorithms
Journal of the ACM (JACM)
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
LRoute: a delay minimal router for hierarchical CPLDs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Communications of the ACM
Proceedings of the 2001 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous short-path and long-path timing optimization for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
ISPD placement contest updates and ISPD 2007 global routing contest
Proceedings of the 2007 international symposium on Physical design
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Timing-driven routing for FPGAs based on Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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As FPGA implementations become more popular in production deployment, improved performance-driven routers are vital in preserving performance upstream from the FPGA design flow. In this paper, a novel long-path timing-driven router, SpiralRoute, is presented. SpiralRoute is a negotiation-based router with a novel path search on a clamped lexicographic spiral cost structure, and provides a guarantee of long-path timing compliance if a legal solution is found. We describe important components of SpiralRoute, including the application of polynomial-time optimal weighted budget distribution to improve connection budget quality, the construction of arbitrary-length lexicographic composition of totally-ordered monoids with order-preserving addition for admissible path search under A*, a trie-of-stacks data structure that allows path candidate extraction and storage to be independent of the size of the index, and a new greedy algorithm for the maintainence of routing tree topology. The efficacy of SpiralRoute is demonstrated by completing 19 instances of long-path timing-driven routing within timing budget that the published timing-driven router VPR 4.30 does not complete. However, SpiralRoute runtimes are slower than VPR 4.30 but we contend that the additional runtime is an acceptable tradeoff for guaranteed solution quality at completion, especially for production circuit routing