LRoute: a delay minimal router for hierarchical CPLDs

Authors:
K. K. Lee;Martin D. F. Wong
Affiliations:
Synopsys, Inc., 700 E. Middlefield Rd, Mountain View, CA;Department of Computer Sciences, The University of Texas at Austin, Austin, TX
Venue:
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Year:
2001

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Abstract

This paper describes LRoute, a novel router for the popular and scalable hierarchical Complex Programmable Logic Devices (CPLDs). CPLD routing has constraints on routing topologies due to architectural limitations and performance considerations. These constraints make the problem quite different from FPGA routing and render the routing problem more complicated. Extensions of popular FPGA routers like the maze router performs poorly on such CPLDs. There is also little published work on CPLD routing. LRoute uses a different paradigm based on the Lagrangian Relaxation framework in the theory of mathematical programming. It respects the topology constraints imposed and routes a circuit with minimum delay. We tested this router on a set of industry problems that commercial software failed to route. Our router was able to route all of them very quickly.