Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Wire synthesizable global routing for timing closure
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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In 2005 and 2006, ISPD successfully hosted two placement contests and released a total of 16 benchmark circuits. These benchmarks are all derived from real industrial circuits and present modern physical design challenges such as scalability, variety of floorplans, movable macro handling, and congestion mitigation. Since their release, the ISPD placement benchmarks have been extensively used by the physical design community. Indeed, we have observed significant progress in placement and floorplanning in the last few years. Much of this success can be credited to the fact that the placement community finally has large, well-defined benchmark circuits available that allow for fair comparisons among different algorithms. In this presentation, we report the most recent results on ISPD placement benchmarks and review how much progress each placement tool has achieved. Continuing the tradition of spirited competition, ISPD 2007 presents a new contest in the global routing area. Similar to previous placement contests, a set of global routing benchmarks are released. These benchmarks are derived from the ISPD placement benchmark solutions; the level of complexity of these benchmarks is comparable to what real industry routing tools encounter. The global routing problem is formulated as a tile-based grid structure superimposed on the chip area; both 2D (single metal layer) and 3D (multiple metal layers) global routing instances will be released. The global routing solutions are evaluated on metrics such as total overflows, maximum overflow of a tile, routed wire length, and the number of vias. CPU time is not included this year to encourage high quality solutions. With placement and global routing benchmarks available, researchers in the fields of placement, floorplanning and global routing should have ample opportunities to attack realistic physical design challenges and contribute their solutions. The placement and global routing contests have attracted strong entries from research groups around the world. In recognition of the importance of the problems, IEEE CEDA and SRC have donated prizes for the winners. Each year of the contest has brought unexpected twists and turns; we anticipate that this and future years will be no different.