Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timing-driven routing for FPGAs based on Lagrangian relaxation
Proceedings of the 2002 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Efficient static timing analysis and applications using edge masks
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Droplet routing in the synthesis of digital microfluidic biochips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A routing approach to reduce glitches in low power FPGAs
Proceedings of the 2009 international symposium on Physical design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A routing approach to reduce glitches in low power FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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This work presents the routing cost valleys (RCV) algorithm - the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a field-programmable gate array (FPGA). RCV is comprised of a new slack allocation algorithm that produces both minimum and maximum delay budgets for each circuit connection, and a new router that strives to meet and, if possible, surpass these connection delay constraints. RCV achieves excellent results. On a set of 100 large circuits, RCV improves both long-path and short-path timing slack significantly vs. an earlier computer-aided design (CAD) system that focuses solely on long-path timing. Even with no short-path timing constraints, RCV improves the clock speed of circuits by 3.9% on average. Finally, RCV is able to meet timing on all 72 peripheral component interconnect (PCI) cores tested, while an earlier algorithm fails to achieve timing on all 72 cores.