Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Delay-optimal technology mapping for FPGAs with heterogeneous LUTs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FPGA logic synthesis using quantified boolean satisfiability
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Small gates, such as AND2, XOR2, and MUX2, have been mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small set logic functions that are able to implement a large portion of functions for given FPGA applications, and propose a heterogeneous PLB with one LUT and one macrogate for the selected logic functions. Furthermore, we develop a synthesis flow for such heterogeneous PLBs, including a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming-based postmapping area recovery to balance the utilization of macrogates and LUTs, and a SAT-based PLB architecture-aware packing. Experiments using over 70 industrial benchmark applications show that we can extract four six-input logic functions to cover more than 50% functions of these applications, and the proposed synthesis flow reduces area by 5% compared to an alternative flow without the postmapping area recovery when both have the optimal logic depth. Compared to the PLB with mixed LUT-4 and small macrogates (XOR2 and MUX2), the PLB with mixed LUT-4 and four-input macrogate reduces logic depth by 6% (and up to 42%) for the aforementioned applications.